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Artesyn ATCA-8310 Installation and Use (May 2014) Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Ausrüstung Artesyn ATCA-8310 Installation and Use (May 2014).
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Artesyn ATCA-8310 Installation and Use (May 2014) Bedienungsanleitung (456 Seiten)


Marke: Artesyn | Kategorie: Ausrüstung | Größe: 27.39 MB |

 

Inhaltsverzeichnis

ATCA-8310

1

Trademarks

2

Contact Address

2

Contents

10

List of Tables

13

List of Figures

23

About this Manual

27

Abbreviations

28

Conventions

32

Summary of Changes

33

Introduction

35

1.2 Standard Compliances

36

1.3 Mechanical Data

39

1.4 Product Identification

39

1.5 Ordering Information

40

Chapter 2

41

LED6LED6

44

LED7LED7

44

2.2.2 Power Requirements

45

2.3 Blade Layout

47

2.4 Switch Settings

48

2.5.1 Installing the Blade

49

2.5.2 Removing the Blade

52

Data Loss

53

Chapter 3

55

3.1 Face Plate

55

3.1.1 LEDs

56

Table 3-1 Face Plate LEDs

57

3.1.2 Keys

58

3.2 Onboard Connectors

60

3.3 ATCA Backplane Connectors

60

3.4 Connector Pin Definitions

62

3.4.2 Zone 3

63

3.4.3 DMC Connector

65

3.4.4 VGA Connector

68

3.4.5 Ethernet Connector

69

3.4.6 Serial Connector

69

3.4.7 USB Connector

70

Zone2UC

72

4.2.1 Memory Interface

73

4.2.1.8 Dual UART

76

4.2.1.9 I2C Interface

76

4.3.1 Intel x86 CPU

78

4.3.1.1 Thermal Monitor

79

4.3.1.2 Chipset Connection

79

4.3.1.3 GPP System Memory

79

4.3.2.8 Ibex-Peak RTC

81

4.4 DSP Farm

82

DSPͲMCConnector

83

4.4.1.1 DSP Configuration

84

4.4.1.2 Boot Mode Selection

84

4.4.1.3 EMAC Boot Mode

84

4.4.2 DSP Memory

85

4.4.3 DSP TSIP Interface

85

4.4.4 SRIO Interface

86

4.4.5 RGMII Interface

86

4.4.6 DSP-FPGA

86

4.4.7 Module IPMC Interface

86

4.5 Ethernet Network (ETH)

89

4.5.2 ETH Switch Unit

90

4.5.3 ATCA Fabric Interface

91

Table 4-8 ACS8520 Frequencies

93

4.6.1 Oscillator

95

4.7 Glue Logic FPGA

96

4.7.1 SPI System Overview

97

4.8 IPMC

99

4.9 Reset Structure

99

4.9.1 Reset Types

100

Functional Description

101

4.9.1.2 SPP-Reset

101

4.9.1.3 Reset Sources

101

4.9.1.4 RTM Reset Behavior

102

Chapter 5

103

5.1 BIOS Considerations

103

5.1.1.2 btorder Parameter

104

5.1.1.3 bootwd Parameter

104

5.1.2 Boot Options

105

5.2 BIOS Operation

106

5.2.2 Boot Process

107

5.2.3 Initiating Setup

107

5.3 Setup Utility

108

5.3.1 Main Menu

110

5.3.1.1 Platform Information

111

5.3.2 Advanced Menu

113

5.3.2.2 ACPI Settings

116

5.3.2.3 Trusted Computing

117

5.3.2.4 S5 RTC Wake Settings

118

5.3.2.5 CPU Configuration

119

5.3.2.6 ME Configuration

122

5.3.2.7 Thermal Configuration

123

5.3.2.8 Port 80h

127

5.3.2.9 TDT Configurations

128

5.3.2.10 USB Configurations

129

5.3.2.11 AMT Configuration

130

Field Description

132

5.3.2.14 Network Stack

137

5.3.3 Chipset Menu

138

5.3.3.2.1 Ibexpeak Options

143

5.3.3.2.2 USB Configuration

144

5.3.3.2.3 SATA Configuration

146

5.3.3.2.5 PCI-to-PCI Bridge

149

5.3.4 Boot Menu

150

5.3.5 Security Menu

151

5.3.6 Save Menu

152

5.4 Status Codes

153

5.4.2 SEC Progress

154

5.4.3 SEC Errors

154

5.4.4 PEI Progress

155

5.4.5 PEI Errors

156

5.4.6 DXE Progress

157

5.4.7 DXE Errors

159

5.4.8 CPU Exceptions

160

5.4.9 ACPI/ASL Checkpoints

161

Chapter 6

163

6.1 Overview

163

6.2 U-Boot

163

6.2.1.2 Environment Variables

164

6.2.1.3 Network interfaces

171

6.2.1.4 GPP Control

171

6.2.1.4.1 GPP Run Levels

172

6.2.1.5 Firmware Update

174

6.2.1.6 FPGA/Logic Operations

174

6.2.1.6.1 Reset Control

175

6.2.1.7 IPMI Interface

176

6.2.1.7.1 FRU Access

177

6.2.1.8 Application Boot

180

 Numerical values

181

6.2.1.8.3 Example

182

6.2.1.9.1 Disk

185

6.2.1.9.2 NFS

185

6.2.1.9.3 RAM Boot (via DHCP)

185

6.2.1.9.4 RAM Boot (No DHCP)

185

6.2.1.10.1 bcm Command

186

6.2.1.11.1 Persistent Memory

190

6.2.1.12 SRIO Initialization

191

6.2.1.13.2 Real-time Clock

194

6.2.1.13.3 fri File Decoding

194

6.2.1.13.4 USB

194

6.2.1.15 Troubleshooting

199

Chapter 7

201

7.1 IPMC Overview

201

7.2 Functional Overview

201

Local Bus

203

7.3 Firmware Architecture

204

 Boot Loader

205

 Active IPMI firmware

205

 Backup IPMI firmware

205

7.5 Sensors

206

7.5.3 POST Results Sensor

207

7.5.4 Power Good Sensor

207

7.5.5 SW Progress Sensors

207

7.5.6 Power Interface Sensors

207

7.5.7 Reset Cause Sensor

208

7.5.8 Presence Sensors

208

7.6 Sensor Data Records

210

Artesyn Pwr Entry

217

7.7 POST

221

7.8 FRU Inventory

221

Length Description

222

Boot Configuration

226

Parameter Storage

226

7.12 Serial Line Selection

228

7.13 Built-in Terminal Server

229

7.14.1 SPP BMC Watchdog

232

7.14.2 SPP FPGA Watchdog

233

7.15 Payload Interface

234

Boot Flash B

235

Boot flash A

235

7.18 FPGA Health Check

236

7.19 GPP THERMTRIP

236

7.21 IPMI Hardware Watchdog

236

7.22 Artesyn OEM Command Set

237

7.22.5 Send SW Progress Data

243

CPLD and FPGA

245

8.1.2 CPLD Registers

246

8.1.3 Reset Structure

257

8.1.4 Clocking Scheme

258

8.1.5 Logic Blocks

258

8.1.5.2 IPMC IRQ

259

8.2 Glue Logic FPGA

261

8.2.1.1 Unit Description

263

8.2.2 Registers

264

8.2.2.1 Register Decoding

265

8.2.3 Logic Blocks

352

8.2.3.3 Super IO Module

354

8.2.3.4 GPP Reset Controller

354

Ibex Peak

355

8.2.3.7 SPP Interrupt Routing

356

8.2.3.8 Hardware Protection

357

8.2.3.15 Serial Redirection

365

8.2.3.16 Reset Domain Control

368

8.2.3.17 Miscellaneous

369

8.3 DSP FPGA

370

8.4 DSP FPGA HW/SW interfaces

372

8.4.3 Logic Blocks

434

8.4.3.7 Debug LEDs

436

Replacing the Battery

439

Related Documentation

443

Safety Notes

445

Installation

446

Operation

447

Switch Settings

448

Environment

448

Sicherheitshinweise

449

Schaltereinstellungen

452

Batterie

453

Umweltschutz

453




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